The present invention relates to voice signal transmission generally and, more particularly, to a dynamic configuration of a time division multiplexing port and associated direct memory access controller.
Time Division Multiplexing (TDM) is a standard protocol used for voice traffic. A typical TDM controller has the capacity to handle hundreds or thousands of channels (or time slots) at a time. Sometimes several TDM ports share one TDM bus in a tri-state structure because one TDM port may not have enough bandwidth. However, at any given time, only a portion of the available time slots are active. Furthermore, previously active channels become inactive and new channels become dynamically active. It is mandatory that this change in configuration not affect any other channels being serviced at the time.
It would be beneficial to save internal bus bandwidth and memory space that is wasted on inactive channels. Further, it would be beneficial to be able to activate and/or deactivate certain time slots of TDM traffic without affecting the transmission or reception of other time slots in a timely manner.
There are several conventional approaches for dealing with TDM port configuration. One conventional approach is to read the data from each and every time slot of the TDM traffic into processor memory. With this approach, inactive channels are not masked. The processor has the responsibility to choose correct (i.e., active) time slots at any given time. However, internal bus bandwidth is wasted on useless data movement for inactive time slots. Another shortcoming with such an approach is that a large amount of processing power is used to extract useful data from the memory.
Another conventional approach is to read the data only for active time slots into processor memory. With this approach, slot masks are used to mask inactive channels. The processor has to update the slot masks after all of the data in the current frame is received or transmitted, but before the next frame starts. This approach is better as far as internal bandwidth utilization is concerned. However, in this scenario, the processor has to update the TDM configuration after the last active time slot of the current frame, but before the first time slot of next frame to ensure that other channels are not affected. This establishes a short timing window for the processor to respond to the change in configuration and process accordingly by setting correct slot masks. In other words, the performance of the TDM traffic controller is limited by the performance of the processor.
It would be desirable to implement a real time TDM port configuration method that (i) does not waste internal bus bandwidth on data movement for inactive time slots, (ii) does not need a large amount of processing power to extract useful data from the memory, and (iii) is not limited in performance by the performance of the processor.
The present invention concerns an apparatus comprising a transmit data path, a receive data path, a first circuit and a second circuit. The first circuit may be configured to transfer data between a first interface and the transmit and receive data paths. The second circuit may be configured (i) to transfer the data between the transmit and receive data paths and a second interface and (ii) to control a configuration update of the first and second circuits in response to a plurality of control signals. The configuration of the first and second circuits is generally dynamically updated.
The objects, features and advantages of the present invention include providing dynamic configuration of a time division multiplexing port and an associated direct memory access controller that may (i) be implemented without interrupting current operation of the TDM port, (ii) offer a level of performance that is independent from the performance of a DSP processor, (iii) be implemented without wasting DSP processing power or internal bus bandwidth in the configuration update, (iv) implement a shadow register to separate the working configuration from the new configuration, (v) implement tag bits associated with the data sample from active time slots to indicate the associated configuration, (vi) control the scheme or flow to select the timing and control the data synchronization of the configuration switch, (vii) reduce MIPS and bandwidth requirement on DSP processors, (viii) make the timing critical task of TDM configuration for DSP processors a non-critical task, (ix) be implemented without limiting the performance of the TDM controller by the performance of the DSP processor, and/or (x) have the potential to serve multiple processors with little modification.